1. Field
Embodiments of the present invention relate to wide-band-gap reverse-blocking MOS-type semiconductor devices which control a high current and a high voltage. Specifically, embodiments of the invention relate to wide-band-gap reverse-blocking MOS-type semiconductor devices which facilitate securing a predetermined breakdown voltage, even if a reverse voltage is applied between the drain and source thereof.
2. Description of the Related Art
Recently, the use of two-way switching devices for matrix converters such as direct-link-type converter circuits has been attracting much attention from the view points of reducing the size thereof, reducing the weight thereof, improving the efficiency thereof, increasing the response speed thereof, and reducing the costs thereof. The direct-link-type converter circuits are used for an AC (alternating current)/AC conversion, an AC/DC (direct current) conversion, and a DC/AC conversion.
The usual inverter/converter combination once converts an AC to an intermediate DC voltage and further converts the intermediate DC voltage to an AC. Since the matrix converter obtains an AC directly from an AC, the power conversion efficiency of the matrix converter is high. Further, the matrix converter is advantageous, since any interposed capacitor is not necessary. Since the inverter/converter combination uses an electrolytic capacitor for the interposed capacitor, it has been troublesome for the life of the inverter/converter combination to be determined by the life of the electrolytic capacitor.
The power device used in the matrix converters is a two-way switching device capable of making a current flow in two directions. The two-way switching device is not configured solely of an elementary transistor. The two-way switching device is configured of two diodes 1002 and two transistors 1001 as described in the equivalent circuit diagram shown in FIG. 16(a). Diode 1002 is connected in series to transistor 1001 in the polarity that facilitates blocking the reverse voltage applied to transistor 1001.
Transistor 1001 as described above includes an insulated-gate bipolar transistor (hereinafter referred to as an “IGBT”) and a metal oxide semiconductor field effect transistor (hereinafter referred to as a “MOSFET”), which are capable of controlling the ON and OFF thereof and conducting the current control with the gate thereof. The diode is connected in series to the transistor, since the usual IGBT and MOSFET are not designed such that the breakdown voltage reliability thereof in the reverse direction is secured. Therefore, the breakdown voltage of the usual IGBT and MOSFET implies the breakdown voltage thereof in the forward direction (hereinafter referred to simply as the “forward bias blocking capability”). Recently, a power device called a “reverse-blocking IGBT” has been developed for improving the reliability of the breakdown voltage in the reverse direction. The reverse-blocking IGBT guarantees a breakdown voltage, when a voltage is applied in the reverse direction, (hereinafter referred to as a “reverse bias blocking capability”) as reliably as the forward withstand voltage.
FIG. 16(b) is the equivalent circuit diagram of a two-way switching device that employs the reverse-blocking IGBT as described above. The two-way switching device in FIG. 16(b) is configured by connecting two reverse-blocking IGBT's 1003 in opposite parallel to each other. As compared with the two-way switching device described in FIG. 16(a), the two-way switching device in FIG. 16(b) facilitates reducing the number of the parts, reducing the power loses, and reducing the size thereof. Therefore, the two-way switching device described in FIG. 16(b) is advantageous for providing a down-sized matrix converter with low manufacturing costs.
FIG. 17 is the cross sectional view of a semiconductor substrate in the reverse-blocking IGBT as described above showing the edge area thereof schematically.
Fundamentally, the configuration of the section that makes a main current flow (active section 40) is the same with that in the conventional IGBT. Emitter electrode 10a is in contact with the p-type base region 2 surface and the n-type emitter region 5a surface and connected electrically to p-type base region 2 and n-type emitter region 5a. Gate electrode 8 is formed above the p-type base region 2 between the n-type emitter region 5a surface and the n−-type drift layer 1 surface with gate insulator film 7 interposed therebetween for configuring a MOS-gate structure.
Collector electrode 12a is formed on collector region 25 formed on the back surface side of the semiconductor substrate such that collector electrode 12a is covering collector region 25 and in electrical contact with collector region 25. In the side wall of the semiconductor substrate, isolation region 24 is formed such that isolation region 24 is in contact with collector region 25 on the back surface side and p-type region 13 on the front surface side and connecting the substrate major surfaces. The pn-junction 14 plane formed by disposing isolation region 24 has a shape that encloses the MOS-gate structure formed in active section 40 of the device. The pn-junction 14 sustains the reverse blocking capability of the device.
When a voltage is applied in the reverse direction (when the voltage applied to emitter terminal 27 is higher than the voltage applied to collector terminal 26), depletion layer 16 represented by the broken lines expands to the n−-type drift layer 1 side as the voltage applied in the reverse direction (hereinafter referred to as the “reverse voltage”) rises. The area, in which the front edge of depletion layer 16 crosses the semiconductor substrate surface, is protected by insulating protector film 18.
The region under the semiconductor substrate surface protected by insulating protector film 18 is breakdown withstanding section 30. The breakdown withstanding structure such as field limiting ring (hereinafter referred to as “FLR”) 17 formed in breakdown withstanding section 30 relaxes the electric field strength, which tends to be high in the vicinity of the semiconductor substrate surface. Due to the relaxation effect, the electric field strength in the vicinity of the semiconductor substrate surface is made to be lower than the electric field strength in the collector junction and the reverse blocking capability of the semiconductor device is made to be more reliable (cf. the following Patent Document 1).
The band gap of silicon carbide (hereinafter referred to sometimes as “SiC”) and gallium nitride (hereinafter referred to sometimes as “GaN”) is about tree times as wide as that of silicon (hereinafter referred to sometimes as “Si”). The Critical Electric field of SiC and GaN is about 10 times as high as that of Si. Therefore, the SiC power device and the GaN power device, exhibiting the same breakdown voltage with that of the Si power device, facilitate switching faster with a lower ON-voltage. In other words, it is possible for the power device that employs SiC or GaN for the substrate material to set the n−-type drift layer 1 thickness (cf. FIG. 17) about one tenth as thick as the n−-type drift layer thickness in the Si power device at the same breakdown voltage.
The n−-type drift layer 1 thickness that provides a vertical SiC power device or a vertical GaN power device with a breakdown voltage of the 1200 V class is around 15 μm. The n−-type drift layer 1 thickness that provides a vertical SiC power device or a vertical GaN power device with a breakdown voltage of the 600 V class is 10 μm or thinner. Since the band gaps of SiC and GaN are wide, the built-in potential of the pn-junction in the SiC power device or the GaN power device will be higher than that of the Si power device, if an IGBT configuration is employed. Therefore, it is hard for the SiC power device and the GaN power device of the 600 V breakdown voltage class or of the 1200 V breakdown voltage class to turn the low ON-voltage to the advantage thereof. Therefore, the manufactures of the SiC device and the GaN device of the above-described breakdown voltage classes have started from the manufactures of the MOSFET and the junction field-effect transistor (hereinafter referred to as the “J-FET”), in which the main current does not flow via the pn-junction in the ON-state of the devices.
However, the MOSFET and the J-FET do not include any junction that sustains the voltage applied in the reverse direction. In other words, the MOSFET and the J-FET do not exhibit the reverse blocking capability characteristics. For applying SiC and GaN to the reverse-blocking device, it may be worthwhile to form a Schottky junction between the drain electrode and the n−-type drift layer. If the junction between the drain electrode and the n−-type drift layer is a Schottky junction, the semiconductor substrate thickness will be the n−-type drift layer thickness, which is from 10 μm to 15 μm, necessary for the SiC device exhibiting a breakdown voltage between 600 V and 1200 V. The resulting semiconductor substrate thickness is too thin to conduct the wafer process without any difficulty.
For obviating the problem described above, the following Patent Document 2 discloses a structure described below. In the disclosed structure, a GaN layer is formed above a thick Si substrate, the resistance thereof is low, via a buffer layer such as an AlN layer interposed between the GaN layer and the Si substrate. A MOS-gate structure is formed in the GaN layer surface. A deep trench, which reaches the GaN layer, is formed from the back surface of the Si substrate layer and a metal electrode for forming a Schottky junction is buried in the deep trench. The trench deep enough to reach the GaN layer is formed from the back surface of Si substrate layer and a metal electrode is buried therein, since it is necessary to bore a hole in the AlN layer, which is an insulator buffer layer.
The following Patent Document 3 discloses a device that has a structure as described below. In the device disclosed in the Patent Document 3, a heavily doped GaN layer and a lightly doped GaN layer are grown epitaxially above a semiconductor substrate in the order of above description with buffer layers interposed between the semiconductor substrate and the heavily doped GaN layer. A trench deep enough to reach the heavily doped GaN layer is formed from the substrate back surface and an electrically conductive material is buried in the trench. However, the GaN MOSFET described in the Patent Document 3 is not a MOSFET that exhibits a reverse blocking capability.
The following Patent Document 4 discloses an IGBT as described below. In the IGBT disclosed in the Patent Document 4, a trench is formed from the substrate back surface. The trench penetrates a collector layer and reaches an n−-type drift layer. An electrically conductive material is buried in the trench. The electrically conductive material is in Schottky contact with the n−-type drift layer. However, the Patent Document 4 describes nothing on the MISFET.
Documents Describing the Related Arts
    [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2002-319676    [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2010-258327    [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2009-54659 (FIG. 7)    [Patent Document 4] U.S. Pat. No. 7,132,321
The Si IGBT has been known to the persons skilled in the art as an elementary switching device that exhibits a reverse bias blocking capability. In the silicon semiconductor device exhibiting a breakdown voltage of the 600 V class or the 1200 V class, the silicon substrate thickness is usually around 100 μm or 200 μm. Therefore, as the breakdown voltage is higher, the tradeoff relation between the ON-voltage and the switching loss is impaired. If the silicon semiconductor device described above is applied to a matrix converter, the efficiency thereof will be impaired or the device will be too large in size to be used practically.
For realizing a reverse blocking capability in the Si reverse-blocking IGBT, it is necessary to form a deep p+-type layer as deep as 100 μm or 200 μm by diffusion. The p+-type layer extends from the n−-type drift layer front surface to the n−-type drift layer back surface. For performing such a deep diffusion as described above, a high temperature and a long diffusion time more than 100 hr are necessary. Therefore, defects are liable to be formed in the n−-type drift layer. Since the lead time of the device manufacture becomes long, the manufacturing efficiency is impaired.
Due to the SiC semiconductor band gap and the GaN semiconductor band gap wider than the Si semiconductor band gap, a large built-in potential is caused, when a current is made to flow in the forward direction. As a result, when a power device exhibiting a breakdown voltage of the 600 V class or the 1200 V class is made of SiC or GaN, the ON-voltage of the power device is too high. Therefore, the SiC power device and the GaN power device are not practical.
For providing the SiC MOSFET, the GaN MOSFET, the SiC J-FET, and the GaN J-FET, exhibiting a breakdown voltage of the 600 V class or the 1200 V class, with a reverse bias blocking capability, it is necessary to form a Schottky junction directly on the n−-type drift layer, the thickness thereof is 10 μm or less or 15 μm (the semiconductor substrate thickness). Therefore, difficulties are caused in the wafer handling in the manufacturing process.
If a deep trench that extends from the Si substrate back surface to the GaN layer is formed and a metal electrode that provides a Schottky junction is buried in the trench as described in the Patent Document 2, many defects will be caused in the GaN layer and it will be hard to obtain a sufficient breakdown voltage.
In view of the foregoing, it would be desirable to provide a wide-band-gap reverse-blocking MOS-type semiconductor device that makes a current high enough for the power device flow with a low ON-state voltage drop and exhibits a very reliable reverse blocking capability, when the wide-band-gap semiconductor materials such as SiC and GaN are used for the main semiconductor substrate material.